View 74GTL1655TTR_1460626.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/14 december 2001 n high speed gtl/gtl+ universal transceiver : t pd = 4.6 ns (max.) a to b at v cc = 3v n combines d-type latches and d-type flip-flops for operation in transparent, latched, or clocked mode n operating voltage range: v cc (opr) = 3.0v to 3.6v n symmetrical output impedance: |i oh | = i ol =24ma (min) at v cc = 3v (a port) n output impedance: i ol = 100ma (min) at v cc = 3v (b port) n high-impedance state during power up and power down up to vcc=1.5v permitt live insertion n b-port precharged by biasvcc reduce noise on the line during live insertion n edge rate-control input configures the b-port output rise and fall times n bus hold on data inputs eliminates the need for external pull-up/ pull-down resistors (a port) n distributed vcc and gnd pin configuration minimizes high-speed switching noise in parallel comunications . n pin and function compatible with 74 series 1655 description the 74gtl1655 devices are 16-bit high-drive (100ma), low-output-impedance universal bus transceivers designed for backplane applications. the 74gtl1655 devices provide live-insertion capability for backplane applications by tolerating active signals on the data ports when the devices are powered off. in addition, a biasing pin preconditions the gtl/gtl+ port to minimize disruption to an active backplane. the edge rate-control (v erc ) input is provided so the rise and fall time of the b outputs can be configured to optimize for various backplane loading conditions. data flow in each direction is controlled by output-enable (oeab and oeba ), 74gtl1655 16 bit lvttl to gtl/gtl + universal bus transceivers with live insertion order codes package tube t & r tssop 74GTL1655TTR tssop pin connection
74gtl1655 2/14 latch-enable (leab and leba), and clock (clk) inputs. for a-to-b data flow, the devices operate in the transparent mode when leab is high. when leab is low, the a data is latched if clk is held at a high or low logic level. if leab is low, the a data is stored in the latch/flip-flop on the low-to-high transition of clk. when oeab is low, the outputs are active. when oeab is high, the outputs are in the high-impedance state. data flow for b to a is similar to that of a to b, but uses oeba , leba, and clk. the output enable (oe ) is used to disable both ports simultaneously. active bus-hold circuitry is provided on the a port to hold unused or floating data inputs at a valid logic level. when v cc is between 0 and 1.5 v, the device is in the high-impedance state during power up or power down. however, to ensure the high-impedance state above 1.5v , oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. all input and output are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. input and output equivalent circuit pin description pin n symbol name and function 1, 2 1oeab , 1oeba output enable input 4, 6, 7, 9, 11, 13, 14, 16 1a1 to 1a8 data inputs/outputs lvttl 17, 19, 20, 22, 23, 25, 27, 29 2a1 to 2a8 data inputs/outputs lvttl 31, 32 2oeab , 2oeba output enable input 33 oe output enable input 34, 35 2leba, 2leab latch enable 36 bias v cc pre-charge supply voltage 37, 38, 40, 42, 43, 45, 46, 48 2b8 to 2b1 data inputs/outputs gtl/gtl+ 41 v ref gtl voltage reference input 49, 51, 52, 54, 55, 56, 58, 59 2a1 to 2a8 data inputs/outputs gtl/gtl+ 61 v erc edge rate control 62, 63 1leba, 1leab latch enable 64 clk clock input (low to high edge triggered) 5, 8, 10, 12, 18, 21, 24, 26, 30, 39, 44, 47, 53, 57, 60 gnd ground (0v) 3, 15, 28, 50 v cc positive supply voltage
74gtl1655 3/14 function table (1) 1) a to b data flow is shown. b to a flow is similar, but uses oeba , leba and clk 2) output level before the indicated steady-state input conditions were established, provided that clk was high before leab wen t low 3) output level before the indicated steady-state input conditions were established output enable truth table b-port edge rate control (v erc ) truth table inputs output mode oeab leab clk a b hxxxziso lation l h x l l transparent l h x h h transparent l l l l registered l l h h registered llhx b0 (2) previous state lllx b0 (3) previous state inputs outputs oe oeab oeba a port b port l l l active active l l h z active l h l active z lhhzz hxxzz input v erc output b port edge rate logic level nominal voltage h v cc slow l gnd fast
74gtl1655 4/14 logic diagram
74gtl1655 5/14 absolute maximum ratings absolute maximum rating are those value beyond which damage to the device may occur. functional operation under these condition is not implied recommended operating conditions 1) v tt and r tt can be adjusted to adapt backplane impedance if dc raccomanded i ol ratings are not exceeded 2) v ref can be adjusted to optimaze noise margin (typ two-thirds v tt ) symbol parameter value unit v cc supply voltage, bias v cc -0.5 to +4.6 v v ia dc input voltage a side, control input -0.5 to +4.6 v v ib dc input voltage b side, v erc , v ref -0.5 to +4.6 v v oa dc output voltage a side -0.5 to +4.6 v v ob dc output voltage b side -0.5 to +4.6 v i ik dc input diode current - 50 ma i ok dc output diode current - 50 ma i oa dc output current a side 48 ma i ob dc output current b side in the low state 200 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit min. typ. max. v cc supply voltage 3.0 3.3 3.6 v v tt termination voltage gtl 1.14 1.2 1.26 v gtl+ 1.35 1.5 1.65 v ref supply voltage gtl 0.74 0.8 0.87 v gtl+ 0.87 1 1.1 v i input voltage b port 0 v tt v other 0 v cc v ih high level input voltage b port v ref +0.05 v other 2 v il low level input voltage b port v ref -0.05 v other 0.8 i ik input clamp current -18 ma i oh high level output current a port -24 ma i ol low level output current a port 24 ma b port 100 dt/dv cc power -up ramp rate 200 m s/v t op operating temperature -40 85 c
74gtl1655 6/14 dc specifications (*) for i/o ports, the parameter i oz includes the input leakage current symbol parameter test condition value unit v cc (v) -40 to 85 c min. typ. max. v ik high level input voltage 3 -1.2 v v oha high level ouput voltage a port 3 to 3.6 i o =-100 m av cc -0.2 v 3 i o =-12ma 2.4 3 i o =-24ma 2.2 v ola low level ouput voltage a port 3 to 3.6 i o =100 m a 0.2 v 3 i o =12ma 0.4 3 i o =24ma 0.55 v olb low level ouput voltage b port 3 i o =40ma 0.2 v 3 i o =80ma 0.4 3 i o =100ma 0.5 i i input current control 3.6 v i = v cc or gnd 10 m a b port 3.6 v i = v tt or gnd 10 m a i off power off leakage current 0v i or v o = 0 to 3.6v 100 m a i i(hold) bus hold a port input current 3 v i = 0.8v 75 20 m a 3 v i = 2v -75 3.6 v i = 0 to v cc 500 i ozhb 3-state output current b port 3.6 v o = 1.5v 10 m a i ozlb 3-state output current b port 3.6 v o = 0.4v -10 m a i oz (*) 3-state output current a port 3.6 v o = v cc or gnd 10 m a i ozpu 3-state output current a port 0 to 1.5 v o = 0.5 to 3v oe = low 50 m a i ozpd 3-state output current a port 1.5 to 0 v o = 0.5 to 3v oe = low 50 m a i cc quiescent supply current 3.6 v i = v cc or gnd i o =0 10 40 ma d i cc d supply current except b port 3.6 v in = v cc or gnd one input v cc =0.6v 1ma c i control input capacitance v in = v cc or gnd 35pf c o input capacitance a port v o = v cc or gnd 56 pf input capacitance b port 6 8
74gtl1655 7/14 live insertion specifications ac electrical characteristics for gtl (v cc =3.3 0.3v, v tt =1.2v, v ref =0.8v, v erc =v cc or gnd) symbol parameter test condition value unit v cc (v) -40 to 85 c min. typ. max. i cc (bias vcc) quiescent bias current 0 to 3.0 v o(bport) = 0 to 1.2v 5 ma 3 to 3.6 v i(bias vcc) = 3 to 3.6v 10 m a v o output voltage b port 0 v i(bias vcc) = 3.3v 1 1.2 v i o output current b port 0 v o(bport) = 0.4v v i(bias vcc) = 3 to 3.6v -1 m a 0 to 3.6 oe = 3.3v 100 m a 0 to 1.5 oe = 0 to 3.3v 100 m a symbol parameter test condition value unit -40 to 85 c min. typ. max. f max maximum frequency a to b or b to a 160 mhz t plh propagation delay time a to b v erc =v cc r 1 =12.5 w c l =30pf 1.5 5.2 ns t phl 1.5 6.2 t plh propagation delay time ck to b v erc =v cc r l =12.5 w c l =30pf 1.5 5.5 ns t phl 1.5 5.8 t plh propagation delay time leab to b v erc =v cc r l =12.5 w c l =30pf 1.5 5.8 ns t phl 1.5 6.4 t en enable delay time oeab or oe to b v erc =v cc r l =12.5 w c l =30pf 1.5 5.4 ns t dis disable delay time oeab or oe to b 1.5 6.2 t plh propagation delay time a to b v erc =gnd r l =12.5 w c l =30pf 1.5 4.3 ns t phl 1.5 4.6 t plh propagation delay time ck to b v erc =gnd r l =12.5 w c l =30pf 1.5 4.3 ns t phl 1.5 4.9 t plh propagation delay time leab to b v erc =gnd r l =12.5 w c l =30pf 1.5 4.9 ns t phl 1.5 4.8 t en enable delay time oeab or oe to b v erc =gnd r l =12.5 w c l =30pf 1.5 4.8 ns t dis disable delay time oeab or oe to b 1.5 4.2 t plh propagation delay time b to a r l =500 w c l =50pf 1.5 4.7 ns t phl 1.5 4.8 t plh propagation delay time ck to a r l =500 w c l =50pf 1.5 4 ns t phl 1.5 4 t plh propagation delay time leba to a r l =500 w c l =50pf 1.5 4 ns t phl 1.5 3.7
74gtl1655 8/14 ac electrical characteristics for gtl + (v cc =3.3 0.3v, v tt =1.5v, v ref =1.0v, v erc =v cc or gnd) t en enable delay time oeba or oe to a r l =500 w r 1 =500 w c l =50pf 1 4.6 ns t dis disable delay time oeba or oe to a 1 6.1 t su set-up time data before clock 2.7 ns data before le ck high 2.8 ck low 2.6 t h hold time data after clock 0.4 ns data after le ck high or low 0.9 t w pulse duration le high 3 ns ck high or low 3 slew rate slew rate b output both transition (0.6 to 1.3v) v erc =v cc 1 ns/v v erc =gnd 1 t sk skew between drivers (in the same package) switching in the same direction 1 ns switching in any direction 1 symbol parameter test condition value unit -40 to 85 c min. typ. max. f max maximum frequency b to a or a to b 160 mhz t plh propagation delay time a to b v erc =v cc r l =12.5 w c l =30pf 1.5 5.1 ns t phl 1.5 6.5 t plh propagation delay time ck to b v erc =v cc r l =12.5 w c l =30pf 1.5 5.4 ns t phl 1.5 6.2 t plh propagation delay time leab to b v erc =v cc r l =12.5 w c l =30pf 1.5 5.7 ns t phl 1.5 6.7 t en enable delay time oeab or oe to b v erc =v cc r l =12.5 w c l =30pf 1.5 5.5 ns t dis disable delay time oeab or oe to b 1.5 5.8 t plh propagation delay time a to b v erc =gnd r l =12.5 w c l =30pf 1.0 4.3 ns t phl 1.0 4.9 t plh propagation delay time ck to b v erc =gnd r l =12.5 w c l =30pf 1.0 4.0 ns t phl 1.0 5.5 t plh propagation delay time leab to b v erc =gnd r l =12.5 w c l =30pf 1.0 4.0 ns t phl 1.0 5.4 t en enable delay time oeab or oe to b v erc =gnd r l =12.5 w c l =30pf 1.0 5.1 ns t dis disable delay time oeab or oe to b 1.0 4.9 symbol parameter test condition value unit -40 to 85 c min. typ. max.
74gtl1655 9/14 t plh propagation delay time b to a r l =500 w c l =50pf 1.5 4.8 ns t phl 1.5 4.7 t plh propagation delay time ck to a r l =500 w c l =50pf 1.5 4.4 ns t phl 1.5 4.1 t plh propagation delay time leba to a r l =500 w c l =50pf 1.5 4 ns t phl 1.5 3.7 t en enable delay time oeba or oe to a r l =500 w r 1 =500 w c l =50pf 1 4.2 ns t dis disable delay time oeba or oe to a 1 6.1 slew rate slew rate b output both transition (0.6 to 1.3v) v erc =v cc r l =12.5 w c l =30pf 1 ns/v v erc =gnd r l =12.5 w c l =30pf 1 t w pulse duration le high 3 ns ck high or low 3 t su set-up time data before clock 2.7 ns data before le ck high 2.8 ck low 2.6 t h hold time data after clock 0.4 ns data after le ck high or low 0.9 t sk skew between drivers (in the same package) switching in the same direction 1 ns switching in any direction 1 symbol parameter test condition value unit -40 to 85 c min. typ. max.
74gtl1655 10/14 test circuit for "a" outputs c l = 50pf or equivalent (includes jig and probe capacitance) r l = r 1 = 500 w or equivalent r t = z out of pulse generator (typically 50 w ) t r =t f <=2.5ns test circuit for "b" outputs c l = 30pf or equivalent (includes jig and probe capacitance) r l = r1 = 12.5 w or equivalent r t = z out of pulse generator (typically 50 w ) t r =t f <=2.5ns test switch t plh, t phl open t pzl, t plz 6v t pzh, t phz gnd
74gtl1655 11/14 waveform 1: pulse duration (a port, control pin) waveform 2: clock to b port propagation delay time waveform 3: clock to a port propagation delay time
74gtl1655 12/14 waveform 4: setup and hold time waveform 4: enable and disable time (a port)
74gtl1655 13/14 dim. mm. inch min. typ max. min. typ. max. a 1.1 0.043 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 d 16.9 17.1 0.665 0.673 e 8.1 0.318 e1 6.0 6.2 0.236 0.244 e 0.5 bsc 0.0197 bsc k0 80 8 l 0.50 0.75 0.020 0.030 tssop64 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7187824a
74gtl1655 14/14 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com

▲Up To Search▲

Price & Availability of 74GTL1655TTR

	To Download 74GTL1655TTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .